1. Field of the invention
The present invention relates to a method of manufacturing a Schottky gate field effect transistor, and more particularly to a method of adjusting the threshold voltage and the drain current of a Schottky gate field effect transistor formed on a compound semiconductor substrate to desired values by making use of an ion implantation method.
2. Description of the Prior Art
A Schottky gate field effect transistor is well known in general as a MESFET (Metal Semiconductor Field-Effect Transistor) as described for example in IEEE ELECTRON DEVICE LETTERS. vol. EDL-4, No. 4 April 1983, PP 102 to 104 by H. M. LEVY and R. E. LEE.
A MESFET is manufactured by forming a refractory-metal gate electrode which serves to provide a Schottky barrier for the implanting of an impurity ion for use in an active layer into a compound semiconductor substrate and annealing the substrate at a temperature of about 800.degree. C., and furthermore, forming an ohmic electrode of the implanting ion into said refractory-metal gate electrode at temperature of about 800.degree. C. to form an n.sup.+ layer. Adjustment of the threshold voltage of such MESFET is effected by changing the amount of implantation of the impurity ion for the active layer described above. Moreover, as disclosed in U.S. Pat. No. 3,912,546, or in U.S. Pat. No. 4,160,984 the threshold voltage, etc., of MESFET is adjusted by implanting an ion into a substrate surface to form crystal defects.
However, it was difficult to form an FET of as desired by use of threshold voltage such prior art semiconductor devices over the whole of the substrate with good reproducibility since there are inevitably produced variations in the characteristics of the compound semiconductor substrates as well as variations in the various conditions thereof in the process of manufacturing. Furthermore, such semiconductor devices, although the threshold voltage of an FET can be measured after forming the usual ohmic electrode, the FET must be heated above beyond 500.degree. C. after the formation of the ohmic electrode, and its characteristics are severly degraded; hence; it is impossible to anneal it at a temperature above 500.degree. C.
In addition, a logical circuit such as an inverter, etc., consists in general of a normally-on type depletion mode FET (hereinafter referred to as D.FET) and of a normally-off type enhancement mode FET (hereinafter referred to as E.FET). Such a D.FET incorporated in the logic circuit is connected at its gate electrode and source electrode with each other and is employed as a constant current source. Here, the saturated drain current (hereinafter referred to as I.sub.D) has the following relationship with and the threshold voltage (hereinafter referred to as V.sub.t): I.sub.D =K(V.sub.G -V.sub.T).sup.2, where V.sub.G is the gate voltage and K is the proportional constant. Accordingly, in employing the D.FET as a constant current source, the relation: I.sub.D =KV.sub.T.sup.2 holds. Here, since K is the proportional constant dependent on the gate length, a gate width the, mobility of the electrons, and the channel thickness, etc., and is typically constant, I.sub.D is controllable in the manufacture of the FET by controlling V.sub.T.
However, it is difficult to form the desired V.sub.T in a circuit design for all substrates with good reproducibility as described before, and with the increased I.sub.D of a D.FET for loading, the current consumed is increased resulting in a reduced noise margin sometimes making logical operation impossible.